Senior Engineer Standard Cells, IOs, Memories & Reliability

• Be responsible for designing and delivering IO and ESD designs from specs to silicon with the relevant deliverables to chip integration team.
• Be involved in IO circuit design, ESD design, device physics and Reliability, IO and ESD Architectures, IO and ESD deliverables, Layout design knowledge, post silicon characterization.

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Requirements:-

• Min 1-4 Years of IO circuit design experience with knowledge of IOs like LVDS, DDR, high speed IOs and GPIO.
• ESD design experience is desirable.
• Have delivered few designs from spec to silicon with complete knowledge associated deliverables.
• Understands importance of timelines.
• Pays attention to details for deliverables quality.
• Team work attitude, good problem-solving communication skills.

Location:-

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• Bangalore, India.