Principal Engineer Standard Cells, IOs, Memories & Reliability

• The successful applicant should have 12+ years of IO circuit design experience with knowledge of IOs like LVDS, DDR, high speed IOs and GPIO. ESD design experience is desirable but no mandatory.
• The applicant will be responsible for designing and delivering IO and ESD designs from specs to silicon with the relevant deliverables to chip integration team.
• Candidate should be able to lead a small team of designers and come up with new architectures and plan schedules

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Candidate Profile:-

• IO circuit design
• ESD design
• Device physics and Reliability
• IO and ESD Architectures
• IO and ESD deliverables
• Layout design knowledge
• Post silicon characterization
• Candidate should have delivered few designs from spec to silicon with complete knowledge associated deliverables.
  Understands importance of timelines.
• Pays attention to details for deliverables quality.
• Team work attitude.
• Good problem solving communication skills

Location:-

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• Bangalore, India.

Company Overview:-